Semiconductor storage units made by large scale integrated circuit techniques have proven to be cost-effective for certain applications of storing digital information. Most storage units are comprised of a plurality of similar storage devices or bit planes, each of which is organized to contain as many storage cells or bits as is feasible in order to reduce per bit costs and to also contain addressing, read and write circuits in order to minimize the number of connections to each storage device. In many designs, this has resulted in an optimum storage device or bit plane that is organized as N words of 1 bit each, where N is some power of two, typically 256, 1,024 or 4,096. Because of the 1 bit organization of the storage device, single bit error correction, double bit error detection as described by Hamming in the publication "Error Detecting and Correcting Codes," R. W. Hamming, The Bell System Journal, Volume XXVI, April 1950, No. 2, Pages 147-160, has proven quite effective in allowing partial or complete failure of a single storage cell or bit in a given word, i.e., a single bit error, the word being of a size equal to the word capacity of the storage device, without causing loss of the data readout from the storage unit. This increases the effective mean-time-between-failure (MTBF) of the storage unit.
Because the storage devices are quite complex, and because many are used in a semiconductor storage unit, they usually represent the predominate component failure in a storage unit. Consequently, it is common practice to employ some form of single bit error correction, double bit error detection along the lines described by Hamming. Also see the publication "Cyclic Codes For Error Detection", W. W. Peterson, et al, Proceedings of the IRE, Vol. 49, January 1961, pages 228-235. While single bit error correction allows for tolerance of storage cell failures, as more of them fail the statistical chance of finding two of them, i.e., a double bit error, in the same word increases. Since two failing storage cells in the same word cannot be corrected without relatively complicated logic as compared with that required by single bit error correction, double bit error detection, it has been the practice to perform regular preventative maintenance upon the storage unit, at which time all replaceable bit planes of the storage unit in which single bit errors have been previously determined would be replaced by new error free bit planes. Such a system utilizes program error logging of the addresses that identify the bit planes that are to be replaced, or, alternatively, the use of error logging stores in which the address of each bit plane in which a single bit error has been detected is logged or stored in a separate buffer memory. Such error logging stores, by assuring proper preventative maintenace procedures, statistically eliminate the possibility of an uncorrectable double bit error in a large scale integrated storage unit using single bit error correction, double bit error detection logic. Such error logging stores in LSI memory storage units are disclosed in my U.S. Pat. No. 3,917,933 and the R. J. Petschauer, U.S. Pat. Nos. 3,906,200 and 3,999,051. Although such error logging stores in LSI semiconductor memory storage units have achieved wide use, it is desirable that double bit error correction, multiple bit error detection (DEC, MED) capabilities be provided if the complex and costly logic usually associated therewith can be avoided. It is, accordingly, a primary object of the present invention to provide such double bit error correction capabilities in a LSI semiconductor memory storage unit while yet avoiding the complex and costly logic that is usually associated with the known prior art double bit error correction techniques.